
#ifndef _IWALE2_REINIT_H_
#define _IWALE2_REINIT_H_

#define NULL  0
#if 0
typedef enum
{
	DDR_CHANNEL_0 = 0,
	DDR_CHANNEL_1 = 1,
}DDR_CHANNEL_NUM_E;

#endif
//------SYS CFG-------

#define FORCE_MODE
#define FORCE_DEEP_SLEEP
//#define AUTO_MODE
//#define MULTI_REGS
//#define TIME_TEST
//#define  LIGHTSLEEP
//#define  MINICODE
//#define RETENTION_FREQ
#define RPULL
//#define DO_TRAINING
#define DDR_TEST
//#define MINICODE

#define CANDS_CTL_REG_BASE	 	0xc0000000
#define CANDS_PI_REG_BASE	 	0xc0000800
#define CANDS_PHY_REG_BASE	 	0xc0002000

#define CANDS_CTL_REG_BASE1	 	0xc0800000
#define CANDS_PI_REG_BASE1	 	0xc0800800
#define CANDS_PHY_REG_BASE1	 	0xc0802000


#define CANDS_CTL0_(i)    (CANDS_CTL_REG_BASE + i*4)
#define CANDS_PI0_(i)     (CANDS_PI_REG_BASE + i*4)
#define CANDS_PHY0_(i)    (CANDS_PHY_REG_BASE + i*4)


#define CANDS_CTL1_(i)    (CANDS_CTL_REG_BASE1 + i*4)
#define CANDS_PI1_(i)     (CANDS_PI_REG_BASE1 + i*4)
#define CANDS_PHY1_(i)    (CANDS_PHY_REG_BASE1 + i*4)


//hosan iwhale2
#define AON_PMU_APB_BASE				0xe42b0000

#define DPLL0_REL_CFG					(AON_PMU_APB_BASE + 0x00d8)
#define DPLL1_REL_CFG					(AON_PMU_APB_BASE + 0x00d0)
#define TWPLL_REL_CFG					(AON_PMU_APB_BASE + 0x00f8)
#define XTLBUF0_REL_CFG				        (AON_PMU_APB_BASE + 0x00ec)
#define XTL0_REL_CFG				        (AON_PMU_APB_BASE + 0x0108)

#define PMU_APB_RF_RPLL1_REL_CFG	      		(AON_PMU_APB_BASE + 0x00e4)
#define PMU_APB_RF_RPLL0_REL_CFG	      		(AON_PMU_APB_BASE + 0x010c)
#define XTLBUF1_REL_CFG					(AON_PMU_APB_BASE + 0x00e0)
#define RC_REL_CFG					(AON_PMU_APB_BASE + 0x0100)

//hosan iwhale2
#define PD_PUB0_SYS_CFG 				(AON_PMU_APB_BASE + 0x0044)
#define PD_PUB1_SYS_CFG 				(AON_PMU_APB_BASE + 0x005c)
#define PD_PUB0_FORCE_SLEEP				(AON_PMU_APB_BASE + 0x012c)
#define PD_PUB1_FORCE_SLEEP				(AON_PMU_APB_BASE + 0x0130)


#define PWR_STATE_DBG1				(AON_PMU_APB_CTL_BASE + 0x011c)
#define PWR_STATE_DBG2				(AON_PMU_APB_CTL_BASE + 0x0120)
#define PWR_STATE_DBG3				(AON_PMU_APB_CTL_BASE + 0x0124)
#define PWR_STATE_DBG4				(AON_PMU_APB_CTL_BASE + 0x0128)

#define PMU_APB_DDR_SLEEP_CTRL 			(0xe42c0008)
#define DDR_PHY_DATA_RET			(0xe42c0048)

#ifdef RUN_CM4
	#define PARA_SAVE_ADDRESS	0x20008000
#else
	#define PARA_SAVE_ADDRESS	0xE601A000
#endif

/*-----------------------------need to ensure---------------------*/

#define PARA_SAVE_SIZE				(64*4)
#define CTL0_REG_SAVE_ADDR			(PARA_SAVE_ADDRESS+PARA_SAVE_SIZE)
#define CTL0_REG_SAVE_SIZE			(481*4)											//iwhale2
#define PI0_REG_SAVE_ADDR			(CTL0_REG_SAVE_ADDR+CTL0_REG_SAVE_SIZE)		//iwhale2
#define PI0_REG_SAVE_SIZE			(249*4)

#define  REG1_SAVE_SIZE				(84*4)		//
#define  REG2_SAVE_SIZE1			(100*4)		//
#define  REG2_SAVE_SIZE2			(38*4)		//

#define PHY0_REG1_SAVE_ADDR_F3			(PI0_REG_SAVE_ADDR+PI0_REG_SAVE_SIZE)			//iwhale2
#define PHY0_REG1_SAVE_SIZE_F3			(84*4)

#define PHY0_REG2_SAVE_ADDR_F3			(PHY0_REG1_SAVE_ADDR_F3+PHY0_REG1_SAVE_SIZE_F3)		//20012620
#define PHY0_REG2_SAVE_SIZE_F3			(1024*4)


#define PHY1_REG1_SAVE_ADDR_F3		(PHY0_REG2_SAVE_ADDR_F3+PHY0_REG2_SAVE_SIZE_F3)		//0x20013F00---1024
#define PHY1_REG2_SAVE_ADDR1_F3		(PHY1_REG1_SAVE_ADDR_F3+REG1_SAVE_SIZE)		//0x20014000---0
#define PHY1_REG2_SAVE_ADDR2_F3		(PHY1_REG2_SAVE_ADDR1_F3+REG2_SAVE_SIZE1)		//0x20014164---128
#define PHY1_REG2_SAVE_ADDR3_F3		(PHY1_REG2_SAVE_ADDR2_F3+REG2_SAVE_SIZE1)		//0x200142C8---256
#define PHY1_REG2_SAVE_ADDR4_F3		(PHY1_REG2_SAVE_ADDR3_F3+REG2_SAVE_SIZE1)		//0x2001442C---384
#define PHY1_REG2_SAVE_ADDR5_F3		(PHY1_REG2_SAVE_ADDR4_F3+REG2_SAVE_SIZE1)		//0x20014590---512
#define PHY1_REG2_SAVE_ADDR6_F3		(PHY1_REG2_SAVE_ADDR5_F3+REG2_SAVE_SIZE2)		//0x20014624---640
#define PHY1_REG2_SAVE_ADDR7_F3		(PHY1_REG2_SAVE_ADDR6_F3+REG2_SAVE_SIZE2)		//0x200146B8---768
#define PHY1_REG2_SAVE_ADDR8_F3		(PHY1_REG2_SAVE_ADDR7_F3+REG2_SAVE_SIZE2)		//0x2001474C---896


#define PHY0_REG1_SAVE_ADDR_F2		(PHY1_REG2_SAVE_ADDR8_F3+REG2_SAVE_SIZE2)		//0x20013F00---1024
#define PHY0_REG2_SAVE_ADDR1_F2		(PHY0_REG1_SAVE_ADDR_F2+REG1_SAVE_SIZE)		//0x20014000---0
#define PHY0_REG2_SAVE_ADDR2_F2		(PHY0_REG2_SAVE_ADDR1_F2+REG2_SAVE_SIZE1)		//0x20014164---128
#define PHY0_REG2_SAVE_ADDR3_F2		(PHY0_REG2_SAVE_ADDR2_F2+REG2_SAVE_SIZE1)		//0x200142C8---256
#define PHY0_REG2_SAVE_ADDR4_F2		(PHY0_REG2_SAVE_ADDR3_F2+REG2_SAVE_SIZE1)		//0x2001442C---384
#define PHY0_REG2_SAVE_ADDR5_F2		(PHY0_REG2_SAVE_ADDR4_F2+REG2_SAVE_SIZE1)		//0x20014590---512
#define PHY0_REG2_SAVE_ADDR6_F2		(PHY0_REG2_SAVE_ADDR5_F2+REG2_SAVE_SIZE2)		//0x20014624---640
#define PHY0_REG2_SAVE_ADDR7_F2		(PHY0_REG2_SAVE_ADDR6_F2+REG2_SAVE_SIZE2)		//0x200146B8---768
#define PHY0_REG2_SAVE_ADDR8_F2		(PHY0_REG2_SAVE_ADDR7_F2+REG2_SAVE_SIZE2)		//0x2001474C---896

#define PHY0_REG1_SAVE_ADDR_F1		(PHY0_REG2_SAVE_ADDR8_F2+REG2_SAVE_SIZE2)		//0x200147E0---1024
#define PHY0_REG2_SAVE_ADDR1_F1		(PHY0_REG1_SAVE_ADDR_F1+REG1_SAVE_SIZE)			//0x200148E0---0
#define PHY0_REG2_SAVE_ADDR2_F1		(PHY0_REG2_SAVE_ADDR1_F1+REG2_SAVE_SIZE1)		//0x20014A44---128
#define PHY0_REG2_SAVE_ADDR3_F1		(PHY0_REG2_SAVE_ADDR2_F1+REG2_SAVE_SIZE1)		//0x20014BA8---256
#define PHY0_REG2_SAVE_ADDR4_F1		(PHY0_REG2_SAVE_ADDR3_F1+REG2_SAVE_SIZE1)		//0x20014D0C---384
#define PHY0_REG2_SAVE_ADDR5_F1		(PHY0_REG2_SAVE_ADDR4_F1+REG2_SAVE_SIZE1)		//0x20014E70---512
#define PHY0_REG2_SAVE_ADDR6_F1		(PHY0_REG2_SAVE_ADDR5_F1+REG2_SAVE_SIZE2)		//0x20014F04---640
#define PHY0_REG2_SAVE_ADDR7_F1		(PHY0_REG2_SAVE_ADDR6_F1+REG2_SAVE_SIZE2)		//0x20014F98---768
#define PHY0_REG2_SAVE_ADDR8_F1		(PHY0_REG2_SAVE_ADDR7_F1+REG2_SAVE_SIZE2)		//0x2001502C---896

#define PHY0_REG1_SAVE_ADDR_F0		(PHY0_REG2_SAVE_ADDR8_F1+REG2_SAVE_SIZE2)		//0x200150C0---1024
#define PHY0_REG2_SAVE_ADDR1_F0		(PHY0_REG1_SAVE_ADDR_F0+REG1_SAVE_SIZE)			//0x200151C0---0
#define PHY0_REG2_SAVE_ADDR2_F0		(PHY0_REG2_SAVE_ADDR1_F0+REG2_SAVE_SIZE1)		//0x20015324---128
#define PHY0_REG2_SAVE_ADDR3_F0		(PHY0_REG2_SAVE_ADDR2_F0+REG2_SAVE_SIZE1)		//0x20015488---256
#define PHY0_REG2_SAVE_ADDR4_F0		(PHY0_REG2_SAVE_ADDR3_F0+REG2_SAVE_SIZE1)		//0x200155EC---384
#define PHY0_REG2_SAVE_ADDR5_F0		(PHY0_REG2_SAVE_ADDR4_F0+REG2_SAVE_SIZE1)		//0x20015750---512
#define PHY0_REG2_SAVE_ADDR6_F0		(PHY0_REG2_SAVE_ADDR5_F0+REG2_SAVE_SIZE2)		//0x200157E4---640
#define PHY0_REG2_SAVE_ADDR7_F0		(PHY0_REG2_SAVE_ADDR6_F0+REG2_SAVE_SIZE2)		//0x20015878---768
#define PHY0_REG2_SAVE_ADDR8_F0		(PHY0_REG2_SAVE_ADDR7_F0+REG2_SAVE_SIZE2)		//0x2001590C------>0x200159a0




#define DDR0_ACC_RDY 				(AON_PMU_APB_CTL_BASE + 0x02cc)
#define DDR1_ACC_RDY 				(AON_PMU_APB_CTL_BASE + 0x02d8)
//hosan iwhale2
#define AON_APB_CTL_BASE                    	0xe42e0000
#define AON_APB_CGM_CFG				(AON_APB_CTL_BASE +0X0098)
#define AON_APB_CGM_REG1			(AON_APB_CTL_BASE +0X0138)
#define AON_APB_CGM_CLK_TOP_REG1		(AON_APB_CTL_BASE +0X013c)

#define AON_APB_PUB_CTRL			(AON_APB_CTL_BASE +0x01e4)
#define EMC_CKG_SEL				AON_APB_PUB_CTRL
#define AON_APB_PUB_FC_CTRL			(AON_APB_CTL_BASE +0X01e0)
#define PUB_FC_CTRL 				(AON_APB_CTL_BASE +0x01E0)
#define AON_RC100M_CFG				(AON_APB_CTL_BASE +0x0134)



#define PAD_OUT_CHIP_SLEEP_CTRL			0xe42c001c		//iwhale2
#define AON_PMU_APB_CTL_BASE			0xe42b0000
#define PD_PUB0_SYS_PWR_CFG     		(AON_PMU_APB_CTL_BASE + 0x0044)
#define PD_PUB1_SYS_PWR_CFG     		(AON_PMU_APB_CTL_BASE + 0x005c)
#define PUB0_FORCE_SLEEP			(AON_PMU_APB_CTL_BASE + 0x012c)
#define PUB1_FORCE_SLEEP			(AON_PMU_APB_CTL_BASE + 0x0130)
#define PD_PUB0_SYS_SHUTDOWN_MARK		(AON_PMU_APB_CTL_BASE + 0x028c)
#define PD_PUB1_SYS_SHUTDOWN_MARK		(AON_PMU_APB_CTL_BASE + 0x02a0)
#define CGM_PMU_SEL				(AON_PMU_APB_CTL_BASE + 0x0234)
#define PD_PUB0_SYS_SHUTDOWN_MARK		(AON_PMU_APB_CTL_BASE + 0x028c)

#define PUB0_SYS_SLEEP_CTRL			(AON_PMU_APB_CTL_BASE + 0x012c)
#define PUB1_SYS_SLEEP_CTRL			(AON_PMU_APB_CTL_BASE + 0x0130)

#define  PREDIV_CLK_REG_BASE  			0xe42d0000
#define  GATE_EN_SEL0_CFG 			(PREDIV_CLK_REG_BASE +0x003c)



#define DDR_SLEEP_CTRL 			0xe42c0008
#ifdef RUN_CM4
	#define TEST_LEN    	0x100000   //1M
	#define TEST_BASE_ADDR1	0x60000000
	#define TEST_BASE_ADDR2 0x61000000
#else
	#define TEST_LEN    	0x100   //64 word
	#define TEST_BASE_ADDR1	0x01000000
	#define TEST_BASE_ADDR2 0x00200000
#endif

void pub0_reinit_handler(uint32 status);

#endif
